LTC2315-12

5

231512f

For more information www.linear.com/2315-12

aDc TiMing characTerisTics

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

(Notes 8, 9)

l

5

MHz

Shift Clock Frequency

(Notes 8, 9)

l

87.5

MHz

Shift Clock Period

l

11.4

ns

l

200

ns

Conversion Time

l

160

ns

Acquisition Time

l

40

ns

Minimum CS Pulse Width

(Note 8)

l

5

ns

SCK Setup Time After CS

↓

(Note 8)

l

5

ns

SDO Enable Time After CS

↓

(Notes 8, 9)

l

6

ns

SDO Data Valid Access Time after SCK

↓

(Notes 8, 9, 10)

l

9.1

ns

SCLK Low Time

l

4.5

ns

SCLK High Time

l

4.5

ns

SDO Data Valid Hold Time After SCK

↓

(Notes 8, 9, 10)

l

1

ns

SDO into Hi-Z State Time After 16th SCK

↓

(Notes 8, 9)

l

3

6

ns

SDO into Hi-Z State Time After CS

↑

(Notes 8, 9)

l

3

6

ns

CS

↑ Setup Time After 14th SCK↓

(Note 8)

l

5

ns

Latency

l

1 Cycle Latency

Power-up Time from Nap Mode

See Nap Mode section

50

ns

See Sleep Mode section

1.1

ms

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. All voltage values are with respect to ground.

diodes. This product can handle input currents up to 100mA below ground

–1dBFS and internal reference unless otherwise noted.

Note 5. Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6. Linearity, offset and gain specifications apply for a single-ended

Note 7. Typical RMS noise at code transitions.

Note 9. All timing specifications given are with a 10pF capacitance load.

Load capacitances greater than this will require a digital buffer.

Note 11. Guaranteed by design, not subject to test.

Note 12. Recommended operating conditions.