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LTC1403A Datasheet(PDF) 5 Page - Linear Technology |
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LTC1403A Datasheet(HTML) 5 Page - Linear Technology |
5 / 20 page LTC2315-12 5 231512f For more information www.linear.com/2315-12 aDc TiMing characTerisTics SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSAMPLE(MAX) Maximum Sampling Frequency (Notes 8, 9) l 5 MHz fSCK Shift Clock Frequency (Notes 8, 9) l 87.5 MHz tSCK Shift Clock Period l 11.4 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 200 ns tCONV Conversion Time l 160 ns tACQ Acquisition Time l 40 ns t1 Minimum CS Pulse Width (Note 8) l 5 ns t2 SCK Setup Time After CS ↓ (Note 8) l 5 ns t3 SDO Enable Time After CS ↓ (Notes 8, 9) l 6 ns t4 SDO Data Valid Access Time after SCK ↓ (Notes 8, 9, 10) l 9.1 ns t5 SCLK Low Time l 4.5 ns t6 SCLK High Time l 4.5 ns t7 SDO Data Valid Hold Time After SCK ↓ (Notes 8, 9, 10) l 1 ns t8 SDO into Hi-Z State Time After 16th SCK ↓ (Notes 8, 9) l 3 6 ns t9 SDO into Hi-Z State Time After CS ↑ (Notes 8, 9) l 3 6 ns t10 CS ↑ Setup Time After 14th SCK↓ (Note 8) l 5 ns Latency l 1 Cycle Latency tWAKE_NAP Power-up Time from Nap Mode See Nap Mode section 50 ns tWAKE_SLEEP Power-up Time from Sleep Mode See Sleep Mode section 1.1 ms The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to ground. Note 3. When these pin voltages are taken below ground or above VDD (AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN = –1dBFS and internal reference unless otherwise noted. Note 5. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6. Linearity, offset and gain specifications apply for a single-ended AIN input with respect to ground. Note 7. Typical RMS noise at code transitions. Note 8. Parameter tested and guaranteed at OVDD = 2.5V. All input signals are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a voltage level of OVDD/2. Note 9. All timing specifications given are with a 10pF capacitance load. Load capacitances greater than this will require a digital buffer. Note 10. The time required for the output to cross the VIH or VIL voltage. Note 11. Guaranteed by design, not subject to test. Note 12. Recommended operating conditions. |
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