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LTC6990 Datasheet(PDF) 7 Page - Linear Technology |
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LTC6990 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 28 page  LTC6995-1/LTC6995-2 7 699512f For more information www.linear.com/6995 Output Resistance vs Supply Current Typical LTC6995-1 Start-Up with POL = 1 Typical perForMance characTerisTics V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. SUPPLY VOLTAGE (V) 699512 G19 50 25 20 35 45 5 10 15 30 40 0 2 4 3 5 6 OUTPUT SOURCING CURRENT OUTPUT SINKING CURRENT V+ 5V/DIV OUT 5V/DIV RST 5V/DIV 5ms/DIV V+ = 5V DIVCODE = 15 RSET = 499k 699512 G20 4ms START-UP OUTPUT RESET RESET RELEASED, 100Hz OUTPUT CLOCK pin FuncTions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup- ply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. An internal A/D converter (referenced to V+) moni- tors the DIV pin voltage (VDIV) to determine a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an ac- curate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pin. SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) pro- grams the master oscillator frequency. The ISET current range is 1.25µA to 20µA. The output oscillation will stop if ISET drops below approximately 500nA. A resistor con- nected between SET and GND is the most accurate way to set the frequency. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/°C or better temperature coefficient. For lower ac- curacy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. 699512 PF LTC6995-1/ LTC6995-2 RST GND SET OUT V+ DIV C1 0.1µF RSET R2 R1 V+ RST or RST (Pin 4/Pin 1): Output Reset. The reset input is used to stop the output oscillator and to clear internal dividers. When reset is released the oscillator starts with a full half period time interval. The output logic state when reset is determined by the programmed DIVCODE. The LTC6995-1 has an active high RST input. The LTC6995-2 has an active low RST input. |
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Similar Description - LTC6990 |
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