 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LT6230 Datasheet(PDF) 8 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LT6230 Datasheet(HTML) 8 Page - Linear Technology |
|
|
8 / 20 page  LTC2315-12 8 231512f For more information www.linear.com/2315-12 TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps, unless otherwise noted. Typical perForMance characTerisTics pin FuncTions VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a 2.2µF ceramic chip capacitor. REF (Pin 2): Reference Input/Output. The REF pin volt- age defines the input span of the ADC, 0V to VREF. By default, REF is an output pin and produces a reference voltage VREF of either 2.048V or 4.096V depending on VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, high quality ceramic chip capacitor. The REF pin may be overdriven with a voltage at least 50mV higher than the internal reference voltage output. GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. SDO (Pin 6): Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with the MSB first through the LSB last. There is 1 cycle of conversion latency. Logic levels are determined by OVDD. SCK (Pin 7): Serial Data Clock Input. The SCK serial clock falling edge advances the conversion process and outputs a bit of the serialized conversion result, MSB first to LSB last. SDO data transitions on the falling edge of SCK. A continuous or burst clock may be used. Logic levels are determined by OVDD. CS (Pin 8): Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer. Bringing CS high places the sample-and-hold into sample mode and also forces the SDO pin into high impedance. Logic levels are determined by OVDD. Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) OUTPUT SUPPLY VOLTAGE (V) 1.7 0 0.5 1.0 2.5 2.0 1.5 2.9 2.3 4.1 3.5 4.7 5.3 231512 G18 5Msps fSCK = 87.5MHz 3Msps fSCK = 52.5MHz Supply Current (IVDD) vs Supply Voltage (VDD) SUPPLY VOLTAGE (V) 2.6 4.50 5.25 5.00 4.75 5.50 5.75 6.00 6.50 6.25 2.9 3.8 3.5 3.2 4.1 4.7 4.4 5.3 5.0 231512 G17 5Msps fSCK = 87.5MHz 3Msps fSCK = 52.5MHz OPERATION NOT ALLOWED 5Msps 3Msps |
Similar Part No. - LT6230 |
|
Similar Description - LT6230 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
