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LTC6991 Datasheet(PDF) 9 Page - Linear Technology

Part # LTC6991
Description  TimerBlox: Long Timer, Low Frequency Oscillator
Download  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC6991 Datasheet(HTML) 9 Page - Linear Technology

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LTC6995-1/LTC6995-2
9
699512f
For more information www.linear.com/6995
operaTion
The LTC6995 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
= 1MHz • 50kΩ •
ISET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
fMASTER =
1
tMASTER
=
1MHz • 50k
RSET
From this equation, it is clear that VSET drift will not affect
theoutputfrequencywhenusingasingleprogramresistor
(RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy ∆fOUT of the LTC6995.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6995 also
includes a programmable frequency divider which can
further divide the frequency by 1, 8, 64, 512, 4096, 215,
218 or 221. The divider ratio NDIV is set by a resistor divider
attached to the DIV pin.
fOUT =
1MHz • 50k
1024 •NDIV
• ISET
VSET
, or
tOUT =
1
fOUT
=
NDIV
50k
• VSET
ISET
• 1.024ms
with RSET in place of VSET/ISET the equation reduces to:
tOUT =
NDIV •RSET
50k
• 1.024ms
DIVCODE
TheDIVpinconnectstoaninternal,V+referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6995:
1. DIVCODE determines the output frequency divider set-
ting, NDIV.
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
699512 F01
LTC6995
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIVandPOLvaluesfortherecommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
=
DIVCODE
+0.5
16
±1.5%
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.


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