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ACT-5231PC-150F22C Datasheet(PDF) 2 Page - Aeroflex Circuit Technology |
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ACT-5231PC-150F22C Datasheet(HTML) 2 Page - Aeroflex Circuit Technology |
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2 / 4 page  Aeroflex Circuit Technology SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700 2 DESCRIPTION The ACT5231 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32KB 2-way set associative instruction cache, a 32KB 2-way set associative data cache, and an efficient 32-bit system interface. The ACT5231 can issue both an integer and a floating point instruction in the same cycle. The ACT5231 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization. HARDWARE OVERVIEW The ACT5231 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the ACT5231 are briefly described below. Superscalar Dispatch The ACT5231 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5231 provides unparalleled price/performance in computationally intensive embedded applications. CPU Registers Like all MIPS ISA processors, the ACT5231 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Pipeline For integer operations, loads, stores, and other non-floating-point operations, the ACT5231 uses the simple 5-stage pipeline also found in the ACT52xx family, R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5231 uses an extended seven stage pipeline for floating-point operations. The ACT5231 does virtual to physical translation in parallel with cache access. Integer Unit The ACT5231 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5231 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5231 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5231 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/ divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter(PC). Register File The ACT5231 has thirty-two general purpose registers with register location 0 hard wired to zero. These registersich allo are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. ALU The ACT5231 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all tions in a single processor cycle. For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark ™ RM 5231™, 32-Bit Superscalar Microprocessor see the latest QED datasheet. |
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