 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ACT-F512K32N-060F5C Datasheet(PDF) 7 Page - Aeroflex Circuit Technology |
|
||||||||||||||||||||||||||||||
ACT-F512K32N-060F5C Datasheet(HTML) 7 Page - Aeroflex Circuit Technology |
|
|
7 / 20 page  A A Aeroflex Circuit Technology SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700 7 timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string. Loading the sector erase buffer may be done in any sequence and with any number of sectors (1 to 8). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. Post Erase data state is all "1"s. The automatic sector erase begins after the 80µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7 is “1" at which time the device returns to read mode. During the execution of the Sector Erase command, only the Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read mode. Data Polling must be performed at an address within any of the sectors being erased. Data Protection The ACT-F512K32 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transitions. During power up the device automatically resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the memory content only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. LOW Vcc WRITE INHIBIT To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for VCC less than 3.2V (typically 3.7V). If VCC <VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2V. WRITE PULSE GLITCH PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding anyone of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. POWER-UP WRITE INHIBIT Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Write Operation Status D7 DATA POLLING The ACT-F512K32 features Data Polling as a method to indicate to the host that the internal algorithms are in progress or completed. During the program algorithm, an attempt to read the device will produce compliment data of the data last written to D7. During the erase algorithm, an attempt to read the device will produce a "0" at the D7 Output. Upon completion of the erase algorithm an attempt to read the device will produce a "1" at the D7 Output. For chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data polling must be performed at a sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the algorithm operation is close to being completed, data pins (D7) change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on D7 at one instance of time and then that byte's valid data at the next instant of time. Depending on when the system samples the D7 Output, it may read the status or valid data. Even if the device has completed internal algorithm operation and D7 has a valid data, the data outputs on D0 - D6 may be still invalid. The valid data on D0 - D7 will be read on the successive read attempts. The Data Polling feature is only active during the programming algorithm, erase algorithm, or sector erase time-out. See Figures 6 and 10 D6 TOGGLE BIT The ACT-F512K32 also features the "Toggle Bit" as a method to indicate to the host system that algorithms are in progress or completed. During a program or erase algorithm cycle, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the program or erase algorithm cycle is completed, D6 Will stop toggling and valid data will be read on successive attempts. During programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse |
Similar Part No. - ACT-F512K32N-060F5C |
|
Similar Description - ACT-F512K32N-060F5C |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
