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ACT-SF512K16N-37F18C Datasheet(PDF) 4 Page - Aeroflex Circuit Technology |
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ACT-SF512K16N-37F18C Datasheet(HTML) 4 Page - Aeroflex Circuit Technology |
4 / 11 page Aeroflex Circuit Technology SCD1663 REV A 4/28/98 Plainview NY (516) 694-6700 4 Timing Diagrams — SRAM DI/O tRC tOH tAA Data Valid Previous Data Valid tOE High Z tOHZ Read Cycle Timing Diagrams Data Valid tCLZ SCE OE tACE tCHZ UNDEFINED DON’T CARE Read Cycle 2 (SWE = VIH) Write Cycle (SCE Controlled, OE = VIH ) tCW tAS tWP tDW tOW SCE SWE Data Valid Write Cycle (SWE Controlled, OE = VIH) DI/O AC Test Circuit IOL Parameter Typical Units Input Pulse Level 0 – 3.0 V Input Rise and Fall 5 ns Input and Output Timing Reference 1.5 V Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75 Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. IOH To Device Under Test VZ ~ 1.5 V (Bipolar Supply) Current Source Current Source CL = 50 pF tWC tAW tAH tRC tAA tOLZ SEE NOTE SEE NOTE SEE NOTE SEE NOTE Note: Guaranteed by design, but not tested. DI/O tDH tWHZ SEE NOTE Read Cycle 1 (SCE = OE = VIL, SWE = VIH) Write Cycle Timing Diagrams tWP tDW Data Valid tWC tAW tAH DI/O tDH SCE SWE tCW tAS A0-18 A0-18 A0-18 A0-18 AC Test Conditions |
Similar Part No. - ACT-SF512K16N-37F18C |
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