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ACT-7000SC-250F17T Datasheet(PDF) 3 Page - Aeroflex Circuit Technology

Part # ACT-7000SC-250F17T
Description  ACT 7000SC 64-Bit Superscaler Microprocessor
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

ACT-7000SC-250F17T Datasheet(HTML) 3 Page - Aeroflex Circuit Technology

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Aeroflex Circuit Technology
SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700
3
The figure illustrates that one F pipe instruction and
one M pipe instruction can be issued concurrently but
that two M pipe or two F pipe instructions cannot be
issued. Table 2 specifies more completely the
instructions within each class.
.
The symmetric superscalar capability of the ACT
7000SC, in combination with its low latency integer
execution units and high-throughput fully pipelined
floating-point execution unit, provides unparalleled
price/performance
in
computational
intensive
embedded applications.
Pipeline
The logical length of both the F and M pipelines is
five stages with state committing in the register write,
or W, pipe stage. The physical length of the
floating-point execution pipeline is actually seven
stages but this is completely transparent to the user.
Figure 3 shows instruction execution within the
ACT 7000SC
when
instructions
are
issuing
simultaneously down both pipelines. As illustrated in
the figure, up to ten instructions can be executing
simultaneously. This figure presents a somewhat
simplistic view of the processors operation however
since the out-of-order completion of loads, stores, and
Figure 2 – Instruction Issue Paradigm
FP
F Pipe
F Pipe IBus
M Pipe IBus
FP
M Pipe
Integer
F Pipe
Integer
M Pipe
Dispatch
Unit
Instruction
Cache
Table 2 – Dual Issue Instruction Classes
integer
load/store
floating-point
branch
add, sub, or, xor,
shift, etc.
lw, sw, ld, sd,
ldc1, sdc1,
mov, movc,
fmov, etc.
fadd, fsub, fmult,
fmadd, fdiv, fcmp,
fsqrt, etc.
beq, bne,
bCzT, bCzF, j,
etc.
I0
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I1
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I2
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I3
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I4
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I5
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I6
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I7
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I8
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
I9
1l
2l
1R
2R
1A
2A
1D
2D
1W
2W
one cycle
1I-1R:
2I:
2R:
1A:
1A:
1A-2A:
2A:
2A-2D:
1D:
2W:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
Figure 3 – Pipeline


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