MT70014

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

4

FUNCTIONAL DESCRIPTION

The device consists of two independent channels each of which functions as a parallel to serial data converter.

The parallel data is loaded via an 8-bit input highway and the serial output is generated in the ARINC

format, i.e. 31 bits of data plus one parity bit.

The input highway (DIO to D17) is common to both channels as are the reset (NRESET) CLOCK 9clock),

input (NLDO), a ‘transmit enable’ input (NTXEO), and a ‘high/low speed’ (HNLO) control input. There are

3 outputs per channel. Channel 0 has a ‘data out zeros’ (ZDO) output, a ‘data out ones’ (ODO) output and a

‘transmission complete’ (TXCO) output.

Operations for Channel 0 and Channel 1 are identical in all respects.

The data to be transmitted by a particular channel is loaded as four 8-bit bytes via the input highway. The

four bytes are stored on chip in the order in which they were loaded. Loading is performed by pulsing the

(NLDO) input low. The data must then be changed to the value of the next byte and (NLDO) pulsed low

again etc.

The four bytes are transmitted in the order in which they were loaded. The only exception is the most

significant bit of the 4th byte. This bit is ignored and a parity bit is transmitted in its place. The parity bit

corresponds to an odd parity check on the first 31 bits, i.e. if the number of ones in the first 31 bits is odd, the

parity bit is equal to zero.

Data is only accepted if the TXCO output is high. Once byte 4 has been loaded, TXCO is driven low. Data

The clock (CLOCK) input of 5mhz + 1%* is divided down on chip by 50 to give a serial data transmission

rate for (HNLO) high or by 380 for (HNLO) low. These rates correspond to the ARINC fast and slow rates

respectively. The timing of the two output data lines (ODO) and (ZDO) is shown in Fig.2. A data value of

one is signified by a positive pulse output on (ODO) and a zero by a positive pulse on (ZDO). The bit period

* ARINC recommends that the transmission rate should not be precisely 100KHZ to avoid interference but

any rate within + 1% of these can be used.

The overall timing diagram for a complete data transfer is shown in Fig.3. When the last byte has been

loaded (TXCO) goes low. This signal is combined with the output of an on chip latch which is set by the

(NTXEO) signal to initiate the start of transmission. The latch is reset upon start of transmission. If the

(NTXEO) signal is left permanently low the on chip latch is always set and transmission will be initiated by

TXCO going low, i.e. as soon as the 4 bytes have been loaded. Hence there is an option between auto-start

and controlled-start of transmission. At the end of the transmission TXCO goes high and the device is able

to accept new data.

The devices can be completely reset by pulsing the (NRESET) line low. This causes both channels to be put

into the data load phase of operation. The TXC lines are forced high and all data outputs are forced low. the

timing is shown in Fig. 4.

INTERFACE DEFINITIONS

The device is implemented as a monolithic circuit using CMOS compatible with standard TLL circuitry.

outputs of the device.