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ACT-7000SC-250F17Q Datasheet(PDF) 7 Page - Aeroflex Circuit Technology |
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ACT-7000SC-250F17Q Datasheet(HTML) 7 Page - Aeroflex Circuit Technology |
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7 / 25 page  Aeroflex Circuit Technology SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700 7 When the ACT 7000SC is configured for 64-bit addressing, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. Joint TLB For fast virtual-to-physical address translation, the ACT 7000SC uses a large, fully associative TLB that maps virtual pages to their corresponding physical addresses. As indicated by its name, the joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as pairs of even/odd entries, and maps a virtual address and address space identifier into the large, 64GB physical address space. By default, the JTLB is configured as 48 pairs of even/odd entries. The 64 even/odd entry optional configuration is set at boot time. Two mechanisms are provided to assist in controlling the amount of mapped space, and the replacement characteristics of various memory regions. First, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4KB to 16MB (in 4X multiples). A CP0 register, PageMask, is loaded with the desired page size of a mapping, and that size is stored into the TLB along with the virtual address when a new entry is written. Thus, operating systems can create special purpose maps; for example, a typical frame buffer can be memory mapped using only one TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The ACT 7000SC provides a random replacement algorithm to select a TLB entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time systems by allowing deterministic access to critical software. The JTLB also contains information that controls the cache coherency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is: uncached, write-back, write-through with write-allocate, write-through without write-allocate, write-back with secondary bypass. Note that both of the write-through protocols bypass the secondary cache since it does not support writes of less than a complete cache line. These protocols are used for both code and data on the ACT 7000SC with data using write-back or write-through depending on the application. The write-through modes support the same efficient frame buffer handling as the RM5200 Family, R4700 and R5000. Instruction TLB The ACT 7000SC uses a 4-entry instruction TLB (ITLB) to minimize contention for the JTLB, to eliminate the critical path of translating through a large associative array, and to save power. Each ITLB entry maps a 4KB page. The ITLB improves performance by allowing instruction address translation to occur in parallel with data address translation. When a miss occurs on an instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the JTLB. The operation of the ITLB is completely transparent to the user. Data TLB The ACT 7000SC uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps a 4KB page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The operation of the DTLB is completely transparent to the user. Figure 5 – Kernel Mode Virtual Addressing (32-bit mode) 0xFFFFFFFF Kernel virtual address space (kseg3) Mapped, 0.5GB 0xE0000000 0xDFFFFFFF Supervisor virtual address space (ksseg) Mapped, 0.5GB 0xC0000000 0xBFFFFFFF Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0xA0000000 0x9FFFFFFF Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x80000000 0x7FFFFFFF User virtual address space (kuseg) Mapped, 2.0GB 0x00000000 |
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