R4430PCP10MCM datasheet(7/11 Pages) AEROFLEX

Part #	R4430PCP10MCM

Description	A MIPS R4400 RISC Microprocessor Multichip Module

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Manufacturer	AEROFLEX [Aeroflex Circuit Technology]

Direct Link	http://www.aeroflex.com

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7

SCD4430 Rev A 11/18/96

Interrupt Interface Signals: These signals comprise the interface used by

external agents to interrupt the R4400 processor

Int(5:1)*

I

Interrupt

: Five of six general processor interrupts, bit-

wise ORed with bits 5:1 of the interrupt register. This

feature available on the R4400PC version only

Int0*

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Interrupt:

One of six general processor interrupts, bit

wise ORed with bit 0 of the interrupt register

NMI*

I

Nonmaskable interrupt

: Nonmaskable interrupt ORed

with bit 6 of the interrupt register

Initialization Interface: These signals comprise the interface by which an

external agent initializes the R4400 operating parameters.

ColdReset*

I

Cold Reset:

This signal must be asserted for a power on

reset or a cold reset. The clocks SClock, TClock, and

RClock begin to cycle and are synchronized with the

de-assertion edge of ColdReset*. ColdReset must be de-

asserted synchronously with MasterOut.

ModeClock

O

Boot Mode Clock:

Serial boot-mode data clock output

at the system clock frequency divided by 256

ModeIn

I

Boot mode data in:

Serial boot-mode data input.

Reset*

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Reset:

This signal must be asserted for any reset

sequence. It may be asserted synchronously or asyn-

chronously for a cold reset, or synchronously to initate

a warm reset. Reset must be de-asserted synchronously

with MasterOut.

VccOk

I

Vcc is OK:

When asserted, this signal tells the R4400

that the 3.3 Volt power supply has been above 3.15

Volts for more than 100 milliseconds & will remain sta-

ble . Assertion of VccOK starts initialization sequence.

256K/1M*

I

Cache size Select:

Must be connected to ground to

enable the full 1M Byte of cache. Cache size will be

256K if pin is left unconnected.

JTAG Interface Signals

JTDI

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JTAG data in:

Data is serial, scanned in thru this pin

JTCK

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JTAG clock input:

The processor outputs a serial clock

on JTCK. On the rising edge of JTCK, both JTDI and

JTMS are sampled.

JTDO

O

JTAG data out:

Data is serial, scanned out thru this pin

JTMS

I

JTAG:

JTAG command signal indicates that the incom-

ming serial data is command clear.

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