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CT2578-12-IN-F84 Datasheet(PDF) 2 Page - Aeroflex Circuit Technology |
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CT2578-12-IN-F84 Datasheet(HTML) 2 Page - Aeroflex Circuit Technology |
2 / 7 page 2 SCDCT2578 REV B 3/11/98 GENERAL DESCRIPTION SIGNAL DESCRIPTIONS CT2578 is for use in simple Remote Terminal applications without the need for a processor or software development. It provides the complete protocol for a Remote Terminal, Signal is connected to the positive side of the external data bus supporting all types of message transfers including all 15 mode codes, with comprehensive error checking. Error handling of data is not required by the subsystem. The user interface is a 16 bit bidirectional highway with a few control lines. The low power transceivers are capable of providing the output voltage required by MIL-STD-1760 and are powered by a +5V supply. If sinusoidal (McAir) transceivers are required then the part number becomes CT2581. This is the only difference between CT2578 and CT2581. A 32 word data buffer memory is used to store messages until validation is complete. Only validated messages are transferred to the subsystem at a rate of 500 nS per word. Data to be transmitted is transferred from the subsystem to this buffer memory at a maximum rate of 1 uS per word. This data memory may be bypassed in the receive mode and data transferred to the subsystem on a word by word basis as it is being received. The device has an optional RT wrap around capability. When WRAPEN is active, data received at subaddress 1E (30) remains stored in the data buffer memory (i.e. not transferred to the subsystem). If followed by a transmit from subaddress 1E the same data will be transmitted. There is an option within the device to reduce the response time in order to conform to other standards such as 1553A and McAir. In this mode subaddress 1F is allocated a normal subaddress with subaddress 00 reserved for mode commands. Any message may be illegalized by applying an active low on the NME discrete status input. The Remote Terminal will respond with the Message Error bit set in the status and not use the information received. A hardware implementation of the 1760 checksum algorithm within the device may be enabled via signal NENCHK. When transmitting, the checksum word is inserted in the last word position, and when receiving, a valid checksum word will generate the open drain output (STATUS). The STATUS output may be hard wired to any of the discrete status inputs (e.g. Service Request), if it is also hard wired to the input NILLCMD the device will respond to a failed checksum with the selected status bit set and not use the data (i.e. not transfer the data to the subsystem). In addition to the signal NVCR (valid command word received) which may be used to illegalize commands, a signal NHDR (header word received) is available to the subsystem for verification of the 1760 message header. The RT address lines are latched on RESET as required by 1760. If all six RT address lines go open circuit the store released signal (STREL) will go high. The device is packaged in a 119 pin grid array or 84 lead CQFP package. 1553 / 1760 DATA BUS DATABUS 0 transformers for bus 0. NDATABUS 0 Signal is connected to the negative side of the external data bus transformers for bus 0. DATABUS 1 Signal is connected to the positive side of the external data bus transformers for bus 1. NDATABUS 1 Signal is connected to the negative side of the external data bus transformers for bus 1. HARD WIRED ADDR A-E (Inputs with pull up resistor) Remote Terminal address inputs for the unit. ADDR A is the least significant bit and ADDR E is the most significant bit. These inputs are internally latched every time the unit is reset. The latched address information is then compared to the incoming command word. ADDR P (Input with pull up resistor) Parity bit for the Remote Terminal address inputs. ADDR P must be set to ODD parity. This input is latched as above. WRAPEN (Input with pull down resistor) Select Remote Terminal wrap around to subaddress 1E. The Bus Controller sends data to subaddress 1E which remains in the data buffer memory and is available to be sent back on the very next command by the Bus Controller. The data in the data buffer memory in this mode does not get transferred to the subsystem. If the very next command is not a transmit command to subaddress 1E, the data buffer memory is flushed and will respond normally to the next set of commands. If the wrap around test is enabled, data to subaddress 1E must be transferred in the correct sequence. “0" = Normal mode “1" = Wrap Around mode MCAIR (Input with pull down resistor) This signal sets the unit to respond with a status word within 4 uS (dead bus time). Subaddress 1F is also enabled to be a valid subaddress for data. Normally subaddress 00 and 1F are reserved for mode codes. “1" = 4 uS dead bus response time, subaddress 1F used for data. “0" = 12 uS response time, subaddress 1F used for mode codes. C16MHZ (Input with pull up resistor) Free running 16 MHZ clock input. SUBSYSTEM INTERFACE T0-T15 (Bibirectional IO) 16 bit bidirectional highway to transfer all information to / from subsystem. The user can also utilise this bus to monitor Command word and Header word (1760 requirement) for message illegalization. |
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