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DNC5X3125 Datasheet(PDF) 3 Page - Agere Systems |
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DNC5X3125 Datasheet(HTML) 3 Page - Agere Systems |
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3 / 18 page  3 Lucent Technologies Inc. Advance Data Sheet DNC5X3125 March 2000 Gigabit Ethernet Transceiver Macrocell Functional Description The DNC5X3125 transceiver provides for data trans- mission over fiber or coaxial media at 1.0 Gbits/s to 1.25 Gbits/s. The block diagram of the macrocell used as a quad-channel transceiver is shown in Figure 1 and the single-channel macrocell design is shown in Figure 2. The input/output designations are given in Table 3. Transmitter Section The typical transmit and receive, high-speed I/O inter- facing for single-channel applications is shown in Figures 8 and 9. The transmitter brings in 8b/10b encoded bits in 10-bit parallel form for up to 1.25 Gbits/s transmission and converts the data to serial format. The serial nonreturn to zero (NRZ) bits are then shifted out of the device at a maximum rate of 1.25 Gbits/s. Internally, the device uses two parallel shift registers that operate at half rate (i.e., a maximum of 625 MHz) for reduced power con- sumption. The two shift registers drive the PECL output buffer in an interleaved manner to construct the 1.25 Gbit/s output data stream. The transmit shift register and other circuits are driven with clocks generated from a 625 MHz internal clock. This internal clock is sourced from a voltage controlled oscillator (VCO) that is locked to the external reference of 100 MHz—125 MHz. The internal transmit phase- lock loop multiplies the frequency of the input reference clock by a factor of 5, and controls the transmit jitter bandwidth with appropriate design of the jitter transfer function. The transmit phase-lock loop generates multi- ple clock phases that are all used by each of the four receiver circuits. The clock phases are derived from the transmit VCO. Receiver Section The receiver circuit extracts clock from and retimes the serial input data. The data are input to the receiver on differential PECL buffers. External termination resistors are supplied by the user in accordance with ANSI stan- dard, X3T11. The serial differential inputs, HDINP and HDINN, are ac-coupled to the device and internally biased to the PECL input common-mode range center. The receiver data-retiming circuit uses a digital timing recovery loop that compares the phase of the input data to multiple phases of the on-device VCO in the transmit section. One of the phases is chosen to retime the receive data. A digital low-pass filter is used in the timing recovery loop to reject jitter from the data input. A novel phase interpolation circuit permits the retiming clock’s phase to be stepped with fine resolution for pre- cise alignment of the sampling clock within the data eye. Use of this digital data-locking scheme for each receiver advantageously avoids the use of multiple analog phase-lock loops on-device that can potentially injection lock to one another. Additionally, the digital data-locking loop maintains precise loop dynamics, hence the jitter transfer function is process and temper- ature independent. Lock to Reference The receive circuit has two modes of operation, lock to reference, and lock to data with retiming. When no data or invalid data is present on the HDINP and HDINN input nodes, the user can program the device to ignore the input data by setting LCKREFN equal to logic 0. In this mode, neither the PECL input buffer nor the RX parallel data bus toggles. In normal operations, LCK- REFN is a logic 1 and the receiver attempts to lock to the incoming data. If the input data is invalid or outside the nominal ± frequency range, the receive digital PLL will simply ramp the phase of the output clock until it locks to data. Table 1. Receiver Circuit Operating Modes* * REFCLK requirements are given in Table 4. Mode Lock to Reference Lock to Receive Data LCKREFN = 1 (normal operation) Not applicable Continually attempts to lock to data. LCKREFN = 0 Lock to clock, output data does not toggle. Disable PECL input buffer. Not applicable. |
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