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BRT1A16E Datasheet(PDF) 4 Page - Agere Systems |
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BRT1A16E Datasheet(HTML) 4 Page - Agere Systems |
4 / 12 page 4 Agere Systems Inc. Data Sheet April 2001 BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Quad Differential Receivers Timing Characteristics Table 4. Timing Characteristics (See Figure 4 and Figure 5.) For propagation delays (tPLH and tPHL) over the temperature range, see Figure 9 and Figure 10. Propagation delay test circuit connected to output is shown in Figure 6. TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V. 12-3462(F) Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to the external capacitance and the intrinsic delay of the device. Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C Parameter Symbol Min Typ Max Unit Propagation Delay: Input to Output High tPLH 1.5 2.5 4.0 ns Input to Output Low tPHL 1.5 2.5 4.0 ns Disable Time, CL = 5 pF: High-to-high Impedance tPHZ —5 12 ns Low-to-high Impedance tPLZ —5 12 ns Pulse Width Distortion, ltpHL − tpLHI: Load Capacitance (CL) = 15 pF tskew1 — — 0.7 ns Load Capacitance (CL) = 150 pF tskew1 — — 4.0 ns Output Waveform Skews: Part-to-Part Skew, TA = 75 °C ∆tskew1p-p — 0.8 1.4 ns Part-to-Part Skew, TA = –40 °C to +125 °C ∆tskew1p-p — — 1.5 ns Same Part Skew ∆tskew — — 0.3 ns Enable Time: High Impedance to High tPZH —8 12 ns High Impedance to Low tPZL —8 12 ns Rise Time (20%—80%) ttLH —— 3.0 ns Fall Time (80%—20%) ttHL —— 3.0 ns 25 50 75 100 125 150 0 LOAD CAPACITANCE, CL (pF) 2 1 3 7 175 200 0 4 5 6 tPHL (TYP) tPLH (TYP) |
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