LCK4801 datasheet(6/10 Pages) AGERE

Part #	LCK4801

Description	Low-Voltage HSTL Differential Clock

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Manufacturer	AGERE [Agere Systems]

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6

Agere Systems Inc.

Preliminary Data Sheet

July 2001

Low-Voltage HSTL Differential Clock

LCK4801

Electrical Characteristics

Table 5. dc Characteristics

VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.

Symbol

Description

Min

Typ

Max

Unit

Condition

VIH

Input High Voltage

2.0

—

VDDD

VLVCMOS

VIL

Input Low Voltage

0.0

—

0.8

V

LVCMOS

VCMR

Input High Voltage1

1. dc levels will vary 1:1 with VDDD.

1—

VDDD – 0.3

V

LVPECL

VPP

Input Low Voltage1

0.5

—

1

V

LVPECL2

2. VPP characteristics required for ac specifications. Actual tolerance of VPP is 200 mV.

VIN (dc)

dc Input Signal Voltage

–0.3

—

1.45

V

HSTL3

3. VIN (dc) specifies maximum dc excursion of each differential input.

VDIF (dc)

dc Differential Input

Voltage

0.4

—

1.75

V

HSTL4

4. The VDIF (dc) minimum is calculated by VOH – VOL, where VOH is the true input signal and VOL is the complementary input signal.

VCM (dc)

dc Common Mode Input

Voltage

0.4

—

1.0

V

HSTL

5

5. VCM specifies the maximum allowable voltage range of the input signal crosspoint.

VOH

Output High Voltage

VX + 0.3

VX + 0.5

1.4

V

HSTL

6,1

6. VX is the differential output crosspoint voltage (see Table 6 on page 7).

VOL

Output Low Voltage

0

VX – 0.5

VX – 0.3

V

HSTL6

IDDI

Core Supply Current

—

140

mA

—

IDDA

PLL Supply Current

—

15

20

mA

—

IDDO

Output Supply Current

—

150

—

mA

—

7

7. Two PCLK signals to 25

Ω, and one EXTFB signal through 50 Ω.

ThetaJA

Junction to Ambient

Thermal Resistance

—53

—

°C/W

—

8

8. 1.3 M/s (250 fpm) airflow.

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