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OR3LP26B Datasheet(PDF) 1 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 1 Page - Agere Systems |
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1 / 184 page  Data Sheet March 2000 ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design imple- mentation, coupled with the high bandwidth of an industry-standard PCI interface. The ORCA OR3LP26B (a member of the Series 3+ FPSC family) provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions. PCI Bus Core Highlights s Implemented in an ORCA Series 3 OR3L125B base array, displacing the bottom ten rows of 28 columns. s Core is a well-tested ASIC model. s Fully compliant to Revision 2.2 of PCI Local Bus specification. s Operates at PCI bus speeds up to 66 MHz on a 32-/64-bit wide bus. s Comprises two independent controllers for Master and Target. s Meets/exceeds all requirements for PICMG* Hot Swap friendly silicon, full Hot Swap model, per the CompactPCI* Hot Swap specification, PICMG 2.1 R1.0. s PCI SIG Hot Plug (R1.0) compliant. s Four internal FIFOs individually buffer both direc- tions of both the Master and Target interfaces: — Both Master FIFOs are 64 bits wide by 32 bits deep. — Both Target FIFOs are 64 bits wide by 16 bits deep. s Capable of no-wait-state, full-burst PCI transfers in either direction, on either the Master or Target interface. The dual 64-bit data paths extend into the FPGA logic, permitting full-bandwidth, simulta- neous bidirectional data transfers of up to 528 Mbytes/s to be sustained indefinitely. s Can be configured to provide either two 64-bit buses (one in each direction) to be multiplexed between Master and Target, or four independent 32-bit buses. s Provides many hardware options in the PCI core that are set during FPGA logic configuration. s Operates within the requirements of the PCI 5 V and 3.3 V signaling environments and 3.3 V com- mercial environmental conditions, allowing the same device to be used in 5 V or 3.3 V PCI sys- tems. s FPGA is reconfigurable via the PCI interface's con- figuration space (as well as conventionally), allow- ing the FPGA to be field-updated to meet late- breaking requirements of emerging protocols. * PICMG and CompactPCI are registered trademarks of the PCI Industrial Computer Manufacturers Group. Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic † The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Device Usable Gates† Number of LUTs Number of Registers Max User RAM Max User I/Os Array Size Number of PFUs OR3LP26B 60K—120K 4032 5304 64K 259 18 x 28 504 |
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