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T7570 Datasheet(PDF) 9 Page - Agere Systems |
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T7570 Datasheet(HTML) 9 Page - Agere Systems |
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9 / 28 page  9 Lucent Technologies Inc. Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter Functional Description (continued) Programmable Functions (continued) Digital Loopback The digital loopback mode is entered by setting the AL and DL bits in the control register as shown in Table 3. This mode provides another stage of path verification by enabling data written into the receive PCM register to be read back from that register in any transmit time slot at DX0/1. In digital loopback mode, the decoder remains functional and outputs a signal at VFRO. If this is undesirable, the receive output can be disabled by programming the receive gain register to all 0s. Interface Latch Directions Immediately following powerup, all interface latches assume they are inputs and, therefore, all IL pins are in a high-impedance state. Each IL pin can be individually programmed as a logic input or output by writing the appropriate instruction to the LDR (see Tables 2 and 5). For minimum power dissipation, unconnected latch pins should be programmed as outputs. Bits L5—L0 must be set by writing the specified instruc- tion to the LDR with the L bits in the second byte set as follows. Table 5. Byte 2 Functions of Latch Direction Register Note: X = don't care. Interface Latch States Interface latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the interface latch register (ILR) as shown in Tables 2 and 6. Latches configured as inputs sense the state applied by an external source, such as the off-hook detect output of a SLIC. All bits of the ILR, i.e., sensed inputs and the pro- grammed state of outputs, can be read back in the sec- ond byte of a read of the ILR. It is recommended that during initialization, the state of IL pins to be configured as outputs should be pro- grammed first, followed immediately by the LDR. Table 6. Interface Latch Data Bit Order Bit Number Time-Slot Assignment The T7570 can operate in either fixed time-slot or time- slot assignment mode for selecting the transmit and receive PCM time slots. Following powerup, the device is automatically in nondelayed timing mode, in which the time slot always begins with the leading (rising) edge of frame-sync inputs FSX and FSR. Time-slot assignment can only be used with delayed-data timing (see Figure 5). FSX and FSR can have any phase rela- tionship with each other in BCLK period increments. Alternatively, the internal time-slot assignment counters and comparators can be used to access any time slot in a frame by using the frame-sync inputs as marker pulses for the beginning of transmit and receive time slots of 8 bits each. A time slot is assigned by a 2-byte instruction as shown in Tables 2 and 7. The last 6 bits of the second byte indicate the selected time slot from 0 to 63 using straight binary notation. A new assign- ment becomes active on the second frame following the end of the for the second control byte. The EN bit allows the PCM inputs, DR0/1, or outputs, DX0/1, as appropriate, to be enabled or disabled. Time-slot assignment mode requires that the FSX and FSR pulses must conform to the delayed-data timing format shown in Figure 5. Port Selection Two transmit serial PCM ports, DX0 and DX1, and two receive serial PCM ports, DR0 and DR1, are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the PS bit in the second byte. Port selection can only be used in delayed-data timing mode. Table 7 shows the format of the second byte of both transmit and receive time-slot and port assignment instructions. Byte 2 Bit Number 76543210 L0 L1 L2 L3 L4 L5 XX Ln Bit IL Direction 0 Input 1 Output Bit Number 76543210 D0 D1 D2 D3 D4 D5 XX CS |
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