T8100A datasheet(3/112 Pages) AGERE

Part #	T8100A

Description	H.100/H.110 Interface and Time-Slot Interchangers

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Advisory

November 1999, Rev. 4

Exceptions and Clarifications for

Ambassador

TM T8100A, T8102,

and T8105 H.100/H.110 Interface and Time-Slot Interchangers

Device Exceptions

Users of the

Ambassador T8100A, T8102, and

T8105 devices should be aware of the following

device operation exceptions and the associated solu-

tions:

1. When a compatibility clock is programmed as a

slave, and the board generates A or B clocks, the

watchdog will indicate an error on the A or B

clocks it generates. The error will be reported

even though the generated clocks are good.

Workaround: Use the master board to accurately

monitor the clocks.

2. When a compatibility clock is programmed as a

slave, and the clock selector is set to A or B

clocks with slide phase alignment, the slave board

does not lock and the generated frame continues

sliding.

Workaround: None.

Product Status: Device redesign required.

3. Models of the

Ambassador T8100A, T8102, and

T8105 devices exhibit intermittent corrupted time-

slot data. H.100 stream 0 time slot 1 (for outgoing

data) and H.100 stream 1 time slot 127 (for

incoming data at 8.192 MHz, time slot 63 for

4.096 MHz, and time slot 31 for 2.048 MHz) are

the most likely stream/time slots to be corrupted.

However, intermittent time-slot corruption may

occur in other stream/time slots.

The time-slot corruption problem occurs when a

T810x device is used in slave-timing mode, as

described in Section 2.5 of the Data Sheet. In a

typical slave timing application, a T810x device is

set to phase align to an incoming bitclock/frame

reference pair (i.e., slave to CT_C8_A/FRAME_A,

CT_C8_B/FRAME_B, C4/FR_COMP, etc.). Both

SNAP and SLIDE alignment modes are affected.

Devices that don't require phase alignment to

these clocks (i.e., the primary bus master) should

not exhibit stream data corruption.

Root Cause: The analog PLL has an error which

introduces an unexpected 6 ns—7 ns of skew.

This skew causes the phase alignment circuit to

fail intermittently, whether in the SNAP or SLIDE

mode. An intermittent SLIDE produces an internal

frame signal that does not align and phase lock

with an incoming frame reference. An intermittent

SNAP forces a reset of the internal counters and

results in corrupted stream data.

Workaround: There is no workaround. The solu-

tion is a fix to the silicon. Samples are scheduled

for release in August 1999.

4. Version 2 models of the

Ambassador T8100A,

T8102, and T8105 devices can exhibit intermittent

corrupted time slot data in one specific configura-

tion. The problem occurs when a master T810x

device is given an 8 kHz signal as the timing

reference and multiplies it up to 2.048 MHz or

4.096 MHz in the digital PLL (DPLL). The DPLL

introduces sufficient jitter on the A or B master

output clocks that slave devices falsely interpret

as a loss of sync and either snap or slide align to

this false sync indication. This, in turn, causes

corruption of time slot data. Any master timing ref-

erence that does not make use of the DPLL does

not exhibit the problem.

Workaround: Do not use an 8 kHz signal as the A

or B master timing reference, since this requires

use of the DPLL. Instead, supply a jitter-free tim-

ing reference at any of the other allowable fre-

quencies (2.048, 4.096, 8.192 or 16.384 MHz).

Product Status: The solution is a fix to the

silicon.

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