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T8302 Datasheet(PDF) 9 Page - Agere Systems |
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T8302 Datasheet(HTML) 9 Page - Agere Systems |
9 / 248 page Table of Contents (continued) Contents Page Agere Systems Inc. 7 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine (ARM ) 13.5.5 Hc LS Threshold Register ........................................................................................................... 176 13.6 Root Hub Partition .................................................................................................................................. 177 13.6.1 Hc Rh Descriptor A Register .......................................................................................................177 13.6.2 Hc Rh Descriptor B Register .......................................................................................................180 13.6.3 Hc Rh Status Register ................................................................................................................. 181 13.6.4 Hc Rh Port Status [1:NDP] Register ............................................................................................ 182 14 IrDA_ACC and UART_ACC ........................................................................................................................... 187 14.1 ACC Operation ....................................................................................................................................... 187 14.1.1 Transmit and Receive Operation ................................................................................................. 188 14.1.2 Transfer Operating Modes .......................................................................................................... 188 14.1.3 Programming the Baud Rate .......................................................................................................188 14.1.4 Extended Characters ...................................................................................................................189 14.2 ACC Registers ....................................................................................................................................... 189 14.2.1 Baud Rate Register ..................................................................................................................... 190 14.2.2 Baud Rate Counter Register .......................................................................................................190 14.2.3 FIFO Status Register ...................................................................................................................191 14.2.4 Receiver Control Register ........................................................................................................... 192 14.2.5 ACC Parity Bit Encoding ............................................................................................................. 192 14.2.6 Transmitter Control Register .......................................................................................................192 14.2.7 Mode Control Register ................................................................................................................ 193 14.2.8 Tx/Rx FIFO Register ...................................................................................................................194 14.2.9 IrDA Feature Register ................................................................................................................. 194 14.3 IrDA Formatter ....................................................................................................................................... 197 14.3.1 IrDA Formatter Operation ............................................................................................................197 14.4 DMA Support for ACC I/O Data ............................................................................................................. 199 14.5 Operation on Reset ................................................................................................................................ 199 15 Synchronous Serial Interface (SSI) ................................................................................................................ 200 15.1 Description .............................................................................................................................................200 15.1.1 Clocks .......................................................................................................................................... 200 15.1.2 Date Transfer .............................................................................................................................. 201 15.1.3 Pin Configuration ......................................................................................................................... 201 15.1.4 SSN Input .................................................................................................................................... 201 15.1.5 Configurations ............................................................................................................................. 201 15.1.6 Slave Chip Select ........................................................................................................................ 202 15.2 SSI Registers ......................................................................................................................................... 203 15.2.1 SSI Data Register ........................................................................................................................ 203 15.2.2 SSI Control Register 1 ................................................................................................................. 204 15.2.3 SSI Control Register 2 Bit Descriptions ....................................................................................... 205 15.2.3.1 SSN ...............................................................................................................................205 15.2.3.2 FASTCLEAR ................................................................................................................. 205 15.2.3.3 MDOD ........................................................................................................................... 205 15.2.3.4 SCOD ............................................................................................................................ 206 15.3 SSI Operation ......................................................................................................................................... 207 15.3.1 SPHA = 0 Format ........................................................................................................................ 208 15.3.1.1 Master Operation ........................................................................................................... 209 15.3.1.2 Slave Operation ............................................................................................................. 209 15.3.2 SPHA = 1 Format ........................................................................................................................ 209 15.3.2.1 Master ........................................................................................................................... 210 15.3.2.2 Slave ............................................................................................................................. 211 15.3.3 Transfer Start .............................................................................................................................. 211 |
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