TTRN012G5 and TTRN012G7

Preliminary Data Sheet

Clock Synthesizer, 16:1 Data Multiplexer

August 2000

8

Lucent Technologies Inc.

Pin Information (continued)

Table 3. Pin Descriptions—Reset and Test Signals

* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.

Table 4. Pin Descriptions—Power and No-Connect Signals

high-frequency filtering is suggested between the individual supplies.

* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.

Pin

Symbol*

Level

Name/Description

40

RESETN

CMOS

Reset (Active-Low). Resets all synchronous logic. During a

reset, the true data outputs are in the low state and the barred

data outputs are in the high state.

0 = reset

1 or no connection = normal operation

6

TSTCKP

I

CML

Test Clock Input. Buffer is powered down when TESTN = 1.

8TSTCKN

10

TESTN

CMOS

Test Clock Select (Active-Low).

0 = select test clock

1 or no connection = select internal VCO

Pin

Symbol*

Level

Name/Description

108, 109, 114,

126, 127

IPower

Analog Power Supply (3.3 V).

2, 3, 5, 7, 9,

12, 20, 24, 29,

34, 35, 48, 51,

54, 63, 70, 80,

90, 104, 107

IPower

Digital Power Supply (3.3 V).

1, 4, 13, 16,

19, 25, 28, 31,

32, 37—39,

55, 58, 64, 65,

75, 85, 95,

100—103,

117—124, 128

GND

I

Ground

Ground.

36, 45, 115,

116, 125

NC

—

—

No Connection. Pin 45 has an internal pull-up resistance

of approximately 25 k

Ω. All of these pins must be left open.