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USS820TD-DB Datasheet(PDF) 6 Page - Agere Systems |
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USS820TD-DB Datasheet(HTML) 6 Page - Agere Systems |
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6 / 58 page  6 Agere Systems Inc. Data Sheet, Rev. 4 June 2001 USB Device Controller USS-820D Description (continued) FIFO Access (continued) Receive FIFO The receive FIFOs are circulating data buffers that have the following features: I Support up to two separate data sets of variable sizes (dual-packet mode). I Include byte count register that accesses the number of bytes in data sets. I Include flags to signal a full FIFO and an empty FIFO. I Can reread the last data set. Figure 3 shows a receive FIFO. A receive FIFO and its associated logic can manage up to two data sets: data set 0 (ds0) and data set 1 (ds1). Since two data sets can be used in the FIFO, back-to-back transmissions are supported. Single-packet mode is established by default after a USS-820D device reset, which sets the RXSPM register bit. Firmware can enable dual-packet mode by clearing the RXSPM bit to 0. The receive FIFO is symmetrical to the transmit FIFO in many ways. The SIE writes to the FIFO location specified by the write pointer. After a write, the write pointer automatically increments by 1. The write marker points to the first byte of data written to a data set, and the read pointer points to the next FIFO location to be read by the CPU. After a read, the read pointer automatically increments by 1. When a good reception is completed, the write marker can be advanced to the position of the write pointer to set up for writing the next data set. When a bad transmission is completed, the write pointer can be reversed to the posi- tion of the write marker to enable the SIE to rewrite the last data set after receiving the data again. The write marker advance and write pointer reversal can be achieved two ways: explicitly by firmware or automatically by hardware, as specified by bits in the receive FIFO control register (RXCON). The CPU should not read data from the receive FIFO before all bytes are received and successfully acknowledged because the reception may be bad. To avoid overwriting data in the receive FIFO, the SIE monitors the FIFO full flag (RXFULL bit in RXFLG). To avoid reading a byte when the FIFO is empty, the CPU can monitor the FIFO empty flag (RXEMP bit in RXFLG). The CPU must not change the value of the EPINDEX register during the process of reading a data set from a par- ticular receive FIFO. Once the CPU has read the first byte of a data set, the processor must ensure that the EPIN- DEX register setting remains unchanged until after the last byte is read from that data set. Registers other than EPINDEX may be read or written during this period, except for registers which affect the overall FIFO configuration, as described in the FIFO Programmability section. If EPINDEX is allowed to change during a data set read, incor- rect data will be returned by the USS-820D when subsequent bytes are read from the partially read data set. There is no such restriction when writing FIFOs. 5-5207 Figure 3. Receive FIFO WRITE POINTER READ POINTER WRITE MARKER RXCNTH RXCNTL BYTE COUNT REGISTERS TO CPU CPU READS FIFO FROM USB INTERFACE DATA SET 0 DATA SET 1 SIE WRITES TO FIFO RXDAT |
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