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100355PC Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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100355PC Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 10 page 5 www.fairchildsemi.com Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack- aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. Symbol Parameter TC = 0°CTC = +25°CTC = +85°C Units Conditions Min Max Min Max Min Max tPLH Propagation Delay tPHL Dna–Dnd to Output 0.60 1.70 0.60 1.70 0.70 1.80 ns (Transparent Mode) tPLH Propagation Delay Figures 1, 2 tPHL S0, S1 to Output 1.00 2.40 1.00 2.40 1.20 2.50 ns (Transparent Mode) tPLH Propagation Delay 0.80 1.80 0.80 1.80 0.80 1.90 ns tPHL E1, E2 to Output tPLH Propagation Delay 0.80 2.10 0.80 2.10 0.80 2.10 ns Figures 1, 3 tPHL MR to Output tTLH Transition Time 0.60 1.30 0.60 1.30 0.60 1.30 ns Figures 1, 2 tTHL 20% to 80%, 80% to 20% tS Setup Time Dna–Dnd 0.80 0.80 0.80 ns Figure 4 S0, S1 1.60 1.60 1.60 MR (Release Time) 1.40 1.40 1.40 Figure 3 tH Hold Time Dna–Dnd 0.30 0.30 0.30 ns Figure 4 S0, S1 −0.10 −0.10 −0.10 tPW (L) Pulse Width LOW E1, E2 2.00 2.00 2.00 ns Figure 2 tPW (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 tOSHL Maximum Skew Common Edge PLCC only Output-to-Output Variation 330 330 330 ps (Note 5) Data to Output Path tOSLH Maximum Skew Common Edge PLCC only Output-to-Output Variation 370 370 370 ps (Note 5) Data to Output Path tOST Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 370 370 370 ps (Note 5) Data to Output Path tPS Maximum Skew PLCC only Pin (Signal) Transition Variation 270 270 270 ps (Note 5) Data to Output Path |
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