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100398PC Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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100398PC Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 13 page www.fairchildsemi.com 2 Logic Symbol Connection Diagrams 24-Pin DIP 28-Pin PLCC Pin Descriptions Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. Pin Names Description E0–E3 ECL Data I/O E0–E3 Complementary ECL Data I/O T0–T3 TTL Data I/O OE Output Enable Input Levels LE Latch Enable Input Levels DIR Direction Control Input (TTL levels) GNDECL ECL Ground GNDECLO ECL Output Ground GNDS ECL Ground-to-Substrate VEE ECL Quiescent Power Supply VEED ECL Dynamic Power Supply GNDTTL TTL Quiescent Ground GNDTTLD TTL Dynamic Ground VTTL TTL Quiescent Power Supply VTTLD TTL Dynamic Power Supply LE DIR OE ECL TTL Notes Port Port 00 0 LOW Z (Cut-Off) 0 0 1 Input Output (Note 1)(Note 4) 01 0 LOW Z (Cut-Off) 0 1 1 Output Input (Note 2)(Note 4) 1 0 0 Input Z (Note 1)(Note 3) 1 0 1 Latched X (Note 1)(Note 3) 1 1 0 Low Input (Note 2)(Note 3) (Cut-Off) 1 1 1 Latched X (Note 2)(Note 3) |
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