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ADV7125KSTZ50 Datasheet(PDF) 8 Page - Analog Devices |
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ADV7125KSTZ50 Datasheet(HTML) 8 Page - Analog Devices |
8 / 16 page ADV7125 Rev. C | Page 8 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 GND GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC NOTES 1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. COMP VAA VAA IOB IOB GND GND 35 VREF 36 34 33 32 31 30 29 28 27 26 25 TOP VIEW (Not to Scale) ADV7125 PIN 1 INDICATOR IOG IOG IOR IOR Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin Number Mnemonic Description 1, 2, 14, 15, 25, 26, 39, 40 GND Ground. All GND pins must be connected. 3 to 10, 16 to 23, 41 to 48 G0 to G7, B0 to B7, R0 to R7 Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plane. 11 BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored. 12 SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. 13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected. 24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. 33, 31, 27 IOR, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If the complementary outputs are not required, these outputs should be tied to ground. 34, 32, 28 IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. 35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. 36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). |
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