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74ACT715-RPC Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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74ACT715-RPC Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 14 page www.fairchildsemi.com 8 RS170 Default Register Values The tables below show the values programmed for the RS170 Format (using a 14.31818 MHz clock signal) and how they compare against the actual EIA RS170 Specifica- tions. The default signals that will be output are CSYNC, CBLANK, HDRIVE and VDRIVE. The device initially starts at the beginning of the odd field of interlace. All signals have active low pulses and the clock is disabled at power up. Registers 13 and 14 are not involved in the actual sig- nal information. If the Vertical Interrupt was selected so that a pulse indicating the active lines would be output. RS170 Horizontal Data Reg D Value H Register Description REG0 0 000 Status Register (715) REG0 1024 400 Status Register (715-R) REG1 23 017 HFP End Time REG2 91 05B HSYNC Pulse End Time REG3 157 09D HBLANK Pulse End Time REG4 910 38E Total Horizontal Clocks REG5 7 007 VFP End Time REG6 13 00D VSYNC Pulse End Time REG7 41 029 VBLANK Pulse End Time REG8 525 20D Total Vertical Lines REG9 57 039 Equalization Pulse End Time REG10 410 19A Serration Pulse Start Time REG11 1 001 Pulse Interval Start Time REG12 19 013 Pulse Interval End Time REG13 41 029 Vertical Interrupt Activate Time REG14 526 20E Vertical Interrupt Deactivate Time REG15 911 38F Horizontal Drive Start Time REG16 92 05C Horizontal Drive End Time REG17 1 001 Vertical Drive Start Time REG18 21 015 Vertical Drive End Time Rate Period Input Clock 14.31818 MHz 69.841 ns Line Rate 15.73426 kHz 63.556 µs Field Rate 59.94 Hz 16.683 ms Frame Rate 29.97 Hz 33.367 ms Signal Width µs %H Specification ( µs) HFP 22 Clocks 1.536 1.5 ±0.1 HSYNC Width 68 Clocks 4.749 7.47 4.7 ±0.1 HBLANK Width 156 Clocks 10.895 17.15 10.9 ±0.2 HDRIVE Width 91 Clocks 6.356 10.00 0.1H ±0.005H HEQP Width 34 Clocks 2.375 3.74 2.3 ±0.1 HSERR Width 68 Clocks 4.749 7.47 4.7 ±0.1 HPER iod 910 Clocks 63.556 100 RS170 Vertical Data VFP 3 Lines 190.67 6 EQP Pulses VSYNC Width 3 Lines 190.67 6 Serration Pulses VBLANK Width 20 Lines 1271.12 7.62 0.075V ± 0.005V VDRIVE Width 11.0 Lines 699.12 4.20 0.04V ± 0.006V VEQP Intrvl 9 Lines 3.63 9 Lines/Field VPERiod (field) 262.5 Lines 16.683 ms 16.683 ms/Field VPERiod (frame) 525 Lines 33.367 ms 33.367 ms/Frame |
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