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XC7SET02GV Datasheet(PDF) 6 Page - NXP Semiconductors |
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XC7SET02GV Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 11 page XC7SET02_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 31 August 2009 6 of 11 NXP Semiconductors XC7SET02 2-input NOR gate 12. Waveforms Measurement points are given in Table 9. Fig 5. The inputs (A and B) to output (Y) propagation delays mna106 A, B input Y output tPHL tPLH VM VM Table 9. Measurement point Type Input Output VI VM VM XC7SET02 GND to 3.0 V 1.5 V 0.5 × VCC Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times mna101 VCC VI VO RT CL PULSE GENERATOR DUT Table 10. Test data Type Input Load Test VI tr, tf CL XC7SET02 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL |
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