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74ACTQ843SPC Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74ACTQ843SPC Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Functional Description The ACTQ843 consists of nine D-type latches with 3- STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asyn- chronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACTQ843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance sys- tems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Inputs Internal Outputs Function CLR PRE OE LE D Q O HHHH L L Z High Z HHHHH H Z High Z H H H L X NC Z Latched H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC Latched H L L X X H H Preset L H L X X L L Clear LLL X X H H Preset L H H L X L Z Clear/High Z HL HL X H Z Preset/High Z |
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