© 2005 Fairchild Semiconductor Corporation

DS500689

www.fairchildsemi.com

October 2001

Revised May 2005

74ALVC16240

Low Voltage 16-Bit Inverting Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16240 contains sixteen inverting buffers with 3-

STATE outputs to be employed as a memory and address

driver, clock driver, or bus oriented transmitter/receiver.

The device is nibble (4-bit) controlled. Each nibble has sep-

arate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74ALVC16240 is designed for low voltage (1.65V to

The 74ALVC16240 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant inputs and outputs

s Power-off high impedance inputs and outputs

s Supports live insertion and withdrawal (Note 1)

s Uses patented noise/EMI reduction circuitry

s Latchup conforms to JEDEC JED78

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Order Number

Package Number

Package Descriptions

74ALVC16240MTD

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names

Description

Output Enable Input (Active LOW)

Inputs

Outputs