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74F646BSC Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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74F646BSC Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 9 page 3 www.fairchildsemi.com Unit Loading/Fan Out Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL A0–A7 Data Register A Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) B0–B7 Data Register B Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA G Output Enable Input 1.0/1.0 20 µA/−0.6 mA DIR Direction Control Input 1.0/1.0 20 µA/−0.6 mA Inputs Data I/O (Note 1) Function G DIR CPAB CPBA SAB SBA A0–A7 B0–B7 H X H or L H or L X X Isolation HX X X X Input Input Clock An Data into A Register HX X X X Clock Bn Data into B Register LH X X LX An to Bn—Real Time (Transparent Mode) LH X L X Input Output Clock An Data into A Register L H H or L X H X A Register to Bn (Stored Mode) LH X H X Clock An Data into A Register and Output to Bn L L XXX L Bn to An—Real Time (Transparent Mode) LL X X L Output Input Clock Bn Data into B Register L L X H or L X H B Register to An (Stored Mode) LL X X H Clock Bn Data into B Register and Output to An |
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