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74LCX16652MEA Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LCX16652MEA Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page February 1994 Revised April 1999 © 1999 Fairchild Semiconductor Corporation DS012005.prf www.fairchildsemi.com 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description The LCX16652 contains sixteen non-inverting bidirectional bus transceivers with 3-STATE outputs providing multi- plexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function (see Func- tional Description). The LCX16652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16652 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s ±24 mA output drive (V CC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Order Number Package Number Package Description 74LCX16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description A0–A15 Data Register A Inputs/3-STATE Outputs B0–B15 Data Register B Inputs/3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs |
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