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74LCX257 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LCX257 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 2000 Fairchild Semiconductor Corporation DS012466 www.fairchildsemi.com May 1995 Revised September 2000 74LCX257 Low Voltage Quad 2-Input Multiplexer with 5V Tolerant Inputs and Outputs General Description The LCX257 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non inverted) form. The outputs may be switched to a high impedance state by placing a logic HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-ori- ented systems. The 74LCX257 is fabricated with advanced CMOS technol- ogy to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 6.0 ns tPD max (VCC = 3.3V, In → Zn), 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LCX257M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description S Common Data Select Input OE 3-STATE Output Enable Input I0a–I0d Data Inputs from Source 0 I1a–I1d Data Inputs from Source 1 Za–Zd 3-STATE Multiplexer Outputs |
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