74LCX574 datasheet(2/14 Pages) FAIRCHILD | Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

2 page

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74LCX574 Rev. 2.0.0

Logic Symbol

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

Pad Assignments for DQFN

(Top View)

Pin Descriptions

Truth Table

= HIGH Voltage Level

= LOW Voltage Level

= Immaterial

= High Impedance

= LOW-to-HIGH Transition

= No Change

Functional Description

The LCX574 consists of eight edge-triggered ﬂip-ﬂops

with individual D-type inputs and 3-STATE true outputs.

The buffered clock and buffered Output Enable are com-

mon to all ﬂip-ﬂops. The eight ﬂip-ﬂops will store the state

of their individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP) tran-

sition. With the Output Enable (OE) LOW, the contents of

the eight ﬂip-ﬂops are available at the outputs. When OE

is HIGH, the outputs go to the high impedance state.

Operation of the OE input does not affect the loading of

the ﬂip-ﬂops.

D0 D1 D2 D3 D4 D5 D6 D7

O1 O2 O3 O4 O5 O6 O7

GND

VCC

GND

VCC

120

Pin Names

Description

D0–D7

Data Inputs

Clock Pulse Input

3-STATE Output Enable Input

O0–O7

3-STATE Outputs

Inputs

Internal Outputs

Function

OE CP

LNCZ

Hold

HNCZ

Hold

Load

Data Available

LNCNC

No Change in Data

HNCNC

No Change in Data

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propaga-

tion delays.

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