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H5TQ2G63BFR-N0C Datasheet(PDF) 4 Page - Hynix Semiconductor |
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H5TQ2G63BFR-N0C Datasheet(HTML) 4 Page - Hynix Semiconductor |
4 / 93 page APCPCWM_4828539:WP_0000002WP_0000002 2. Command Description 2.1 Command Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3. Absolute Maximum Ratings 4. Operating Conditions 4.1 Operating Temperature Condition 4.2 DC Operating Conditions 5. AC and DC Input Measurement Levels 5.1 AC and DC Logic Input Levels for Single-Ended Signals 5.2 AC and DC Logic Input Levels for Differential Signals 5.3 Differential Input Cross Point Voltage 5.4 Slew Rate Definitions for Single Ended Input Signals 5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) 5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) 5.5 Slew Rate Definitions for Differential Input Signals 6. AC and DC Output Measurement Levels 6.1 Single Ended AC and DC Output Levels 6.1.1 Differential AC and DC Output Levels 6.2 Single Ended Output Slew Rate 6.3 Differential Output Slew Rate 6.4 Reference Load for AC Timing and Output Slew Rate 7. Overshoot and Undershoot Specifications 7.1 Address and Control Overshoot and Undershoot Specifications 7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 7.3 34 ohm Output Driver DC Electrical Characteristics 7.4 Output Driver Temperature and Voltage sensitivity *33ed5962-ee6c* B20337/178.104.2.234/2010-08-26 09:03 |
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