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PA28F200B5B80 Datasheet(PDF) 10 Page - Intel Corporation |
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PA28F200B5B80 Datasheet(HTML) 10 Page - Intel Corporation |
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10 / 44 page  28F200B5, 28F004/400B5, 28F800B5 E 10 PRELIMINARY 28F004B5 Boot Block 40-Lead TSOP 10 mm x20mm TOP VIEW 32 31 30 29 28 27 26 25 24 23 22 21 33 34 35 36 37 38 39 40 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 A 1 A 2 A 3 RP# WE# VPP A16 A15 A7 A6 A5 A4 A14 A13 A8 A9 A11 A12 WP# DQ7 CE# OE# GND A0 DQ6 DQ5 DQ4 DQ2 DQ1 DQ0 VCC DQ3 A17 GND NC A10 NC NC A18 VCC Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only) 2.3 Memory Blocking Organization The boot block product family features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. At automotive temperature, each parameter block can be erased independently 30,000 times, and each main and boot block 1,000 times. The block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. The combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. For the address locations of the blocks, see the memory maps in Figures 4, 5, 6 and 7. 2.3.1 ONE 16-KB BOOT BLOCK The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller- based system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to accommodate different microprocessor protocols for boot code location. This boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the VPP, RP#, and WP# pins, as is detailed in Section 3.3. 2.3.2 TWO 8-KB PARAMETER BLOCKS Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the byte-rewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel’s application note, AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM. The parameter blocks are not write-protectable. 2.3.3 MAIN BLOCKS - ONE 96-KB + ADDITIONAL 128-KB BLOCKS After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each device contains one 96-Kbyte (98,304 byte) block and additional 128-Kbyte (131,072 byte) blocks. The 2-Mbit has one 128-KB block; the 4-Mbit, three; and the 8-Mbit, seven. |
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