© 2000 Fairchild Semiconductor Corporation

DS500236

www.fairchildsemi.com

January 2000

Revised January 2000

74VCX162373

Low Voltage 16-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

and 26

Ω Series Resistors in Outputs

General Description

The VCX162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

The VCX162373 is also designed with 26

Ω resistors in the

outputs. This design reduces line noise in applications

such as memory address drivers, clock drivers and bus

transceivers/transmitters.

The 74VCX162373 is designed for low voltage (1.65V to

The 74VCX162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant inputs and outputs

s 26

Ω series resistors in outputs

s Power-off high impedance inputs and outputs

s Support live insertion and withdrawal (Note 1)

±12 mA @ 3.0V V

CC

±8 mA @ 2.3V V

CC

±3 mA @ 1.65V V

CC

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 300 mA

s ESD performance:

Human body model

> 2000V

Machine model

> 200V

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Ordering Number

Package

Package Description

Number

74VCX162373MTD

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names

Description

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

Outputs