MPC2104

•MPC2105•MPC2106•MPC2107

3

MOTOROLA FAST SRAM

MPC2104/MPC2105 BLOCK DIAGRAM

MCM67Mx18

A15

K

G

E

DQ0 – DQ8

A13

STANDBY

TSC

COE0

TSP

A14 – A26

VCC5 via 100 Ω

A2 – A14

A14 – A26

LW

BAA

ADS0

CWE0

A2 – A12

A1

TCLR

TWE

CLK2

MATCH

DIRTYOUT

VALIDIN

DIRTYIN

TOE

TAG: 16K x 12 + V + D

A13

RESET

A0 – A12

TAG, TAD, E2

SFUNC, SG

TDQ0 – TDQ10

TDQ11

SW

TW

K

MATCH

DIRTYQ

VALIDD

DIRTYD

TG

CLK3

= NC

CLK4

= NC

ALE

= NC

ADS1

= NC

CNTEN1

= NC

COE1

= NC

ADDR0

= NC

ADDR1

= NC

PD2

= NC

PD3

J0

X24C00

(OPTIONAL)

SCL

SDA

PD0/IDSCLK

PD1/IDSDATA

J2

J3

DQ9 – DQ17

UW

CLK0

DH0 – DH7 + DP0

DH8 – DH15 + DP1

CWE1

CNTEN0

A1

A27

A0

A28

MCM67Mx18

A15

K

G

E

DQ0 – DQ8

TSC

TSP

A2 – A14

LW

BAA

CWE2

DQ9 – DQ17

UW

CLK0

DH16 – DH23 + DP2

DH24 – DH31 + DP3

CWE3

A1

A0

MCM67Mx18

A15

K

G

E

DQ0 – DQ8

TSC

TSP

A2 – A14

LW

BAA

CWE4

DQ9 – DQ17

UW

CLK1

DL0 – DL7 + DP4

DL8 – DL15 + DP5

CWE5

A1

A0

MCM67Mx18

A15

K

G

E

DQ0 – DQ8

TSC

TSP

A2 – A14

LW

BAA

CWE6

DQ9 – DQ17

UW

CLK1

DL16 – DL23 + DP6

DL24 – DL31 + DP7

CWE7

A1

A0

’244

TT1, WTD, E1

TAH, PWRDN

J5

VSS

VCC5 via 100 Ω

WTQ

VALIDQ

VCCQ

VCC3

NC

256KB

512KB

EEPROM

EEPROM

256KB

512KB

J5

no stuff

0

Ω

no stuff

0

Ω

J4

0

Ω

0

Ω

no stuff

no stuff

J3

0

Ω

0

Ω

no stuff

no stuff

J2

0

Ω

no stuff

no stuff

no stuff

J1

0

Ω

no stuff

0

Ω

no stuff

J0

no stuff

0

Ω

no stuff

0

Ω

J4

J1

Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.

NC