MPC2104P

•MPC2105P

6

MOTOROLA FAST SRAM

Next Cycle

Address

Used

Standby

ADS0

CNTEN0

CG0 2

DHx/DLx

CWEx 2

Deselect

None

1

0

X

X

High–Z

X

Begin Read

External

0

0

X

X

High–Z

14

Continue Read

Next

X

1

0

1

High–Z

1

Continue Read

Next

X

1

0

0

DQ

1

Suspend Read

Current

X

1

1

1

High–Z

1

Suspend Read

Current

X

1

1

0

DQ

1

Begin Write

External

0

0

X

X

High–Z

0

Continue Write

Next

X

1

0

X

High–Z

0

Suspend Write

Current

X

1

1

X

High–Z

0

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. CG0 is an asynchronous signal and is not sampled by the clock CLK0. CG0 drives the bus immediately (tGLQX) following CG0 going low.

3. On write cycles that follow read cycles, CG0 must be negated prior to the start of the write cycle to ensure proper write data setup times.

CG0 must also remain negated at the completion of the write cycle to ensure proper write data hold times.

4. This READ assumes the RAM was previously deselected.

ASYNCHRONOUS TRUTH TABLE

Operation

CG0

I/O Status

Read

L

Data Out (DHx/DLx)

Read

H

High–Z

Write

X

High–Z

Deselected

X

High–Z

Sleep

X

High–Z

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00