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MT41J256M8 Datasheet(PDF) 10 Page - Micron Technology |
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MT41J256M8 Datasheet(HTML) 10 Page - Micron Technology |
10 / 211 page Table 51: DDR3-1066 Speed Bins ................................................................................................................... 71 Table 52: DDR3-1333 Speed Bins ................................................................................................................... 72 Table 53: DDR3-1600 Speed Bins ................................................................................................................... 73 Table 54: DDR3-1866 Speed Bins ................................................................................................................... 74 Table 55: DDR3-2133 Speed Bins ................................................................................................................... 75 Table 56: Electrical Characteristics and AC Operating Conditions .................................................................... 76 Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 86 Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 96 Table 59: Derating Values for tIS/tIH – AC175/DC100-Based ............................................................................ 97 Table 60: Derating Values for tIS/tIH – AC150/DC100-Based ............................................................................ 97 Table 61: Derating Values for tIS/tIH – AC135/DC100-Based ............................................................................ 98 Table 62: Derating Values for tIS/tIH – AC125/DC100-Based ............................................................................ 98 Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition ............................... 99 Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 104 Table 65: Derating Values for tDS/tDH – AC175/DC100-Based ........................................................................ 105 Table 66: Derating Values for tDS/tDH – AC150/DC100-Based ........................................................................ 105 Table 67: Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns ........................................................... 106 Table 68: Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns ........................................................... 107 Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ......................... 108 Table 70: Truth Table – Command ................................................................................................................. 113 Table 71: Truth Table – CKE .......................................................................................................................... 115 Table 72: READ Command Summary ............................................................................................................ 117 Table 73: WRITE Command Summary .......................................................................................................... 117 Table 74: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 123 Table 75: Write Leveling Matrix ..................................................................................................................... 127 Table 76: Burst Order .................................................................................................................................... 136 Table 77: MPR Functional Description of MR3 Bits ........................................................................................ 146 Table 78: MPR Readouts and Burst Order Bit Mapping ................................................................................... 147 Table 79: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 179 Table 80: Self Refresh Mode Summary ........................................................................................................... 179 Table 81: Command to Power-Down Entry Parameters .................................................................................. 180 Table 82: Power-Down Modes ....................................................................................................................... 181 Table 83: Truth Table – ODT (Nominal) ......................................................................................................... 191 Table 84: ODT Parameters ............................................................................................................................ 191 Table 85: Write Leveling with Dynamic ODT Special Case .............................................................................. 192 Table 86: Dynamic ODT Specific Parameters ................................................................................................. 193 Table 87: Mode Registers for RTT,nom ............................................................................................................. 193 Table 88: Mode Registers for RTT(WR) ............................................................................................................. 194 Table 89: Timing Diagrams for Dynamic ODT ................................................................................................ 194 Table 90: Synchronous ODT Parameters ........................................................................................................ 199 Table 91: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 204 Table 92: ODT Parameters for Power-Down (DLL Off ) Entry and Exit Transition Period ................................... 206 2Gb: x4, x8, x16 DDR3 SDRAM Features PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. |
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