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74VHCT138A Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74VHCT138A
Description  3-to-8 Decoder/Demultiplexer
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Maker  FAIRCHILD [Fairchild Semiconductor]

 1 page
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June 1997
Revised April 1999
© 1999 Fairchild Semiconductor Corporation
3-to-8 Decoder/Demultiplexer
General Description
The VHCT138A is an advanced high speed CMOS 3-to-8
DECODER fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
When the device is enabled, 3 Binary Select inputs (A0, A1
and A2) determine which one of the outputs (O0–O7) will go
LOW. When enable input E3 is held LOW or either E1 or E2
is held HIGH, decoding function is inhibited and all outputs
go HIGH. E3, E1 and E2 inputs are provided to ease cas-
cade connection and for use as an address decoder for
memory systems. Protection circuits ensure that 0V to 7V
can be applied to the input pins without regard to the sup-
ply voltage and to the output pins with VCC = 0V. These cir-
cuits prevent device destruction due to mismatched supply
and input/output voltages. This device can be used to inter-
face 3V to 5V systems and two supply systems such as
battery backup.
s High Speed: tPD = 7.6 ns (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max.) at TA = 25°C
s Power down protection is provided on all inputs and
s Pin and function compatible with 74HCT138
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Address Inputs
Enable Inputs
Enable Input

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