September 1996

BSS100 / BSS123

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

Features

_______________________________________________________________________________

Absolute Maximum Ratings

T

Symbol

Parameter

BSS100

BSS123

Units

V

DSS

Drain-Source Voltage

100

V

V

DGR

Drain-Gate Voltage (R

100

V

V

GSS

Gate-Source Voltage - Continuous

± 14

V

- Non Repetitive (T

± 20

I

D

Drain Current - Continuous

0.22

0.17

A

- Pulsed

0.9

0.68

P

D

Total Power Dissipation @ T

0.63

0.36

W

T

Operating and Storage Temperature Range

-55 to 150

°C

T

L

Maximum Lead Temperature for Soldering

Purposes, 1/16" from Case for 10 Seconds

300

°C

THERMAL CHARACTERISTICS

Thermal Resistacne, Junction-to-Ambient

200

350

°C/W

BSS100 Rev. F1 / BSS123 Rev. F1

These N-Channel logic level enhancement mode power

field effect transistors are produced using Fairchild's

proprietary, high cell density, DMOS technology. This

very high density process has been especially tailored to

minimize on-state resistance, provide superior switching

performance. This product is particularly suited to low

voltage, low current applications, such as small servo

motor controls, power MOSFET gate drivers, and other

switching applications.

BSS100: 0.22A, 100V. R

BSS123: 0.17A, 100V. R

High density cell design for extremely low R

Voltage controlled small signal switch.

Rugged and reliable.

BSS123

S

D

G

BSS100

© 1997 Fairchild Semiconductor Corporation