MPC974

MOTOROLA

TIMING SOLUTIONS

BR1333 — Rev 6

6

the voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20KHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it’s overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL.

Although the MPC974 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

adequate to eliminate power supply noise related problems

in most designs.

Driving Transmission Lines

The MPC974 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 10

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions brochure (BR1333/D).

Figure 5. Single versus Dual Transmission Lines

7

Ω

IN

MPC974

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutA

7

Ω

IN

MPC974

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutB0

RS = 43Ω

ZO = 50Ω

OutB1

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC974 clock driver. For the

series terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated lines.

Figure 5 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC974 clock

driver is effectively doubled due to its capability to drive

multiple lines.

The waveform plots of Figure 6 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC974 output buffers is

more than sufficient to drive 50

Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC974. The output waveform

in Figure 6 shows a step in the waveform, this step is caused

by the impedance mismatch seen looking into the driver. The

parallel combination of the 43

Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

Figure 6. Single versus Dual Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.8V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 7 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.