© 2000 Fairchild Semiconductor Corporation

DS006282

www.fairchildsemi.com

April 1984

Revised March 2000

DM74AS74

Dual D-Type Positive-Edge-Triggered Flip-Flop

with Preset and Clear

General Description

The AS74 is a dual edge-triggered flip-flops. Each flip-flop

has individual D, clock, clear and preset inputs, and also

complementary Q and Q outputs.

Information at input D is transferred to the Q output on the

positive going edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not

directly related to the transition time of the positive going

pulse. When the clock input is at either the HIGH or LOW

level, the D input signal has no effect.

Asynchronous preset and clear inputs will set or clear Q

output respectively upon the application of LOW level sig-

nal.

Features

s Switching specifications at 50 pF

s Switching specifications guaranteed over full tempera-

s Advanced oxide-isolated, ion-implanted Schottky TTL

process

s Functionally and pin-for-pin compatible with Schottky

and LS TTL counterpart

s Improved AC performance over S74 at approximately

half the power

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

L

= LOW State

H

= HIGH State

X

= Don't Care

↑ = Positive Edge Transition

Note 1: This condition is nonstable; it will not persist when preset and clear

inputs return to their inactive (HIGH) level. The output levels in this condi-

Order Number

Package Number

Package Description

DM74AS74M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74AS74SJX

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74AS74N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

PR

CLR CLK

D

Q

Q

LH

X

X

H

L

HL

X

X

L

H

L

L

X

X

H (Note 1)

H (Note 1)

HH

↑

HH

L

HH

↑

LL

H

HH

L

X