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IS45S16160G-7TLA2 Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS45S16160G-7TLA2 Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
2 / 63 page 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/20/2012 IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-accessmemorydesignedtooperatein3.3VVdd and3.3VVddq memorysystemscontaining268,435,456 bits.Internallyconfiguredasaquad-bankDRAMwitha synchronousinterface.Each67,108,864-bitbankisorga- nizedas8,192rowsby512columnsby16bitsor8,192 rowsby1,024columnsby8bits. The256MbSDRAMincludesanAUTOREFRESHMODE, andapower-saving,power-downmode.Allsignalsare registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The256MbSDRAMhastheabilitytosynchronouslyburst dataatahighdataratewithautomaticcolumn-address generation,theabilitytointerleavebetweeninternalbanks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burstaccess. Aself-timedrowprechargeinitiatedattheendoftheburst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Prechargeonebankwhileaccessingoneofthe otherthreebankswillhidetheprechargecyclesandprovide seamless,high-speed,random-accessoperation. SDRAMreadandwriteaccessesareburstorientedstarting ataselectedlocationandcontinuingforaprogrammed number of locations in a programmed sequence.The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE commandinconjunctionwithaddressbitsregisteredare usedtoselectthebankandrowtobeaccessed(BA0, BA1selectthebank;A0-A12selecttherow).TheREAD or WRITE commands in conjunction with address bits registeredareusedtoselectthestartingcolumnlocation fortheburstaccess. ProgrammableREADorWRITEburstlengthsconsistof 1,2,4and8locationsorfullpage,withaburstterminate option. CLK CKE CS RAS CAS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A10 A12 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQML DQMH DQ 0-15 VDD/VDDQ Vss/VssQ 13 13 9 13 13 9 16 16 16 16 512 (x 16) 8192 8192 8192 8192 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER A11 2 FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx16x4 BANKS SHOWN) |
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