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AT25020B-MAHL-T Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT25020B-MAHL-T Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 27 page 7 8707B–SEEPR–3/10 AT25010B/020B/040B 3. Functional Description The AT25010B/020B/040B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Figure 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Note: “A” represents MSB address bit A8. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All program- ming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 3-1. Instruction Set for the AT25010B/020B/040B Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 A011 Read Data from Memory Array WRITE 0000 A010 Write Data to Memory Array Table 3-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XXXX BP1 BP0 WEN RDY Table 3-3. Read Status Register Bit Definition Bit Definition Bit0(RDY) Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 3-4. Bit 3 (BP1) See Table 3-4. Bits 4–7 are “0”s when device is not in an internal write cycle. Bits 0–7 are “1”s during an internal write cycle. |
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