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IS45S16160G-7BLA2 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS45S16160G-7BLA2 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
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1 / 63 page  IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 3/20/2012 Copyright©2012IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewith- outnotice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtain thelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts. IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcan reasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchap- plicationsunlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that: a.)theriskofinjuryordamagehasbeenminimized; b.)theuserassumeallsuchrisks;and c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances FEATURES • Clockfrequency:166,143MHz • Fullysynchronous;allsignalsreferencedtoa positiveclockedge • Internalbankforhidingrowaccess/precharge • SinglePowersupply:3.3V+0.3V • LVTTLinterface • Programmableburstlength –(1,2,4,8,fullpage) • Programmableburstsequence: Sequential/Interleave • AutoRefresh(CBR) • SelfRefresh • 8Krefreshcyclesevery32ms(A2grade)or 64ms(commercial,industrial,A1grade) • Randomcolumnaddresseveryclockcycle • ProgrammableCASlatency(2,3clocks) • Burstread/writeandburstread/singlewrite operationscapability • Burstterminationbyburststopandprecharge command OPTIONS • Package: 54-pinTSOP-II 54-ballBGA • OperatingTemperatureRange: Commercial(0oCto+70oC) Industrial(-40oCto+85oC) AutomotiveGradeA1(-40oCto+85oC) AutomotiveGradeA2(-40oCto+105oC) OVERVIEW ISSI's256MbSynchronousDRAMachieveshigh-speed datatransferusingpipelinearchitecture.Allinputsand outputssignalsrefertotherisingedgeoftheclockinput. The256MbSDRAMisorganizedasfollows. 32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM MARCH 2012 IS42S83200G IS42S16160G 8Mx8x4Banks 4Mx16x4Banks 54-pinTSOPII 54-pinTSOPII 54-ballBGA 54-ballBGA Parameter 32M x 8 16M x 16 Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks Refresh Count Com./Ind. A1 A2 8K/64ms 8K/64ms 8K/16ms 8K/64ms 8K/64ms 8K/16ms Row Addresses A0-A12 A0-A12 Column Addresses A0-A9 A0-A8 Bank Address Pins BA0, BA1 BA0, BA1 Auto Precharge Pins A10/AP A10/AP ADDRESS TABLE KEY TIMING PARAMETERS Parameter -6 -7 Unit ClkCycleTime CAS Latency=3 6 7 ns CAS Latency=2 10 7.5 ns ClkFrequency CAS Latency=3 166 143 Mhz CASLatency=2 100 133 Mhz AccessTimefromClock CAS Latency=3 5.4 5.4 ns CAS Latency=2 6.5 5.4 ns |
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