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AZ809ANLTR-G1 Datasheet(PDF) 8 Page - BCD Semiconductor Manufacturing Limited |
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AZ809ANLTR-G1 Datasheet(HTML) 8 Page - BCD Semiconductor Manufacturing Limited |
8 / 11 page Data Sheet 3-PIN MICROPROCESSOR RESET CIRCUIT AZ809A 8 Oct. 2010 Rev. 1. 3 BCD Semiconductor Manufacturing Limited Application Information The AZ809A asserts a reset signal LOW whenever the VCC supply voltage is below the threshold voltage and remains asserted for 240ms typically after the VCC has risen above the threshold. Operating Diagram Valid RESET with VCC under 1.0 V The AZ809A RESET output is valid to VCC=1.0V. Below this voltage, the output becomes an open circuit and doesn't sink current. Therefore, high-impedance CMOS logic input connected to RESET can drift to undetermined voltages. To ensure that the AZ809A RESET is in a known state when VCC is under 1.0V, a 100KΩ pull-down resistor between the RESET pin and GND is recommended to discharge stray capacitances and maintain the output low. VCC AZ809A RESET GND R1 100k Ω Figure 11. Reset Timing Diagram of AZ809A Figure 12. RESET Valid to VCC=0V 240ms Typical VTH VCC 240ms Typical Time 20 µs Typical Reset Active Timeout Period Output Undefined RESET Time VCC (min) |
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