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DM93S41N Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part # DM93S41N
Description  4-Bit Arithmetic Logic Unit
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM93S41N Datasheet(HTML) 2 Page - Fairchild Semiconductor

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Functional Description
The DM93S41 is a 4-bit high speed parallel arithmetic logic
unit (ALU). Controlled by the four Function Select inputs
(S0–S3) and the Mode Control input (M), it can perform all
the 16 possible operations or 16 different arithmetic opera-
tions on active HIGH or active LOW operands. The Func-
tion Table below lists these operations.
When the Mode Control input (M) is HIGH, all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control
input is LOW, the carries are enabled and the device per-
forms arithmetic operations on the two 4-bit words. The
device incorporates full internal carry lookahead and pro-
vides for either ripple carry between devices using the Cn+4
output, or for carry lookahead between packages using the
signals P (Carry Propagate) and G (Carry Generate). P
and G are not affected by carry in. When speed require-
ments are not stringent, the DM93S41 can be used in a
simple ripple carry mode by connecting the Carry output
(Cn+4) signal to the Carry input (Cn) of the next unit. For
super high speed operation the Schottky DM93S41 should
be used in conjunction with the '42 carry lookahead circuit.
The A
= B output from the DM93S41 goes HIGH when all
four Fn outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A
= B output is open-collector and can be wired-
AND with the other A
= B outputs to give a comparison for
more than four bits. The A
= B signal can also be used with
the Cn+4 signal to indicate A > B and A < B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied.
Because subtraction is actually performed by complemen-
tary addition (1s complement), a carry out means borrow;
thus a carry is generated when there is no underflow and
no carry is generated when there is underflow.
As indicated the '41 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the oper-
ands labeled inside the logic symbol.
Function Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
Note 1: Each bit is shifted to the next more significant position
Note 2: Arithmetic operations expressed in 2s complement notation
Mode Select
Active LOW Inputs
Active HIGH Inputs
Inputs
& Outputs
& Outputs
Logic Arithmetic (Note 2)
Logic Arithmetic (Note 2)
S3
S2
S1
S0
(M
= H)
(M
= L) (C
n = L)
(M
= H)
(M
= L) (C
n = H)
LL
LL
A
A minus 1
A
A
LL
L
H
AB
AB minus 1
A
+ B
A
+ B
LL
H
L
A
+ B
AB minus 1
ABA
+ B
L
L
H
H
Logic 1
minus 1
Logic 0
minus 1
LH
L
L
A
+ B
A plus (A
+ B)AB
A plus AB
LH
L
H
B
AB plus (A
+ B)B
(A
+B) plus AB
LH
H
L
A
⊕ B
A minus B minus 1
A
⊕ B
A minus B minus 1
L
HHH
A
+ B
A
+ B
AB
AB minus 1
HL
L
L
ABA plus (A
+ B)
A
+ B
A plus AB
HL
L
H
A
⊕ B
A plus B
A
⊕ B
A plus B
HL
HL
B
AB plus (A
+ B)
B
(A
+ B) plus AB
HL
H
H
A
+ BA + B
AB
AB minus 1
H
H
L
L
Logic 0
A plus A (Note 1)
Logic 1
A plus A (Note 1)
HH
L
H
AB
AB plus A
A
+ B
(A
+ B) plus A
H
H
H
L
AB
AB minus A
A
+ B(A + B) plus A
H
H
H
H
AA
AA minus 1


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