Manual Reset Outputs

_______________________________________________________________________________________

7

Applications Information

Interrupt Before Reset

To minimize data loss and speed system recovery/test,

many applications interrupt the processor or reset only

portions of the system before a processor hard reset is

asserted. The extended setup time of the MAX6455/

MAX6456 MR input allows the same pushbutton (Figure

4) to control both the interrupt and hard reset functions.

If the pushbutton is closed for less than the extended

setup timeout period, the processor is only interrupted

(MROUT). If the system still does not respond properly,

the pushbutton can be closed for the full extended

setup timeout period to hard reset the processor

(RESET). If desired, connect a LED to the RESET output

to turn off (or on) to signify when the pushbutton is

closed long enough for a hard reset (the same LED can

be used as the front panel power-on display).

Interfacing to Other Voltages

for Logic Compatibility

The open-drain RESET output can be used to interface

to a µP with other logic levels. As shown in Figure 5, the

open-drain output can be connected to voltages from 0

to 6V.

Generally, the pullup resistor connected to the RESET

connects to the supply voltage being monitored at the

open-drain output to level-shift from the monitored sup-

ply to reset circuitry powered by some other supply

decreases toward 1V, so does the IC’s ability to sink

toward 0). The voltage where this occurs depends on

the pullup resistor value and the voltage to which it is

connected.

Ensuring a Valid

(Push-Pull

RESET)

bilities decline drastically. The high-impedance CMOS-

logic inputs connected to RESET can drift to

undetermined voltages. This presents no problem in

most applications, because most µPs and other circuit-

In applications where RESET must be valid down to 0V,

add a pulldown resistor between RESET and GND for

the push/pull outputs. The resistor sinks any stray leak-

age currents, holding RESET low (Figure 6). The value

of the pulldown resistor is not critical; 100k

Ω is large

enough not to load RESET and small enough to pull

RESET to ground. The external pulldown cannot be

used with the open-drain reset outputs.

Transient Immunity

In addition to issuing a reset to the µP during power-up,

power-down and brownout conditions, these supervisors

are relatively immune to short duration falling transients

(glitches). The graph Maximum Transient Duration vs.

Reset Threshold Overdrive in the Typical Operating

Characteristics section shows this relationship.

The area below the curves of the graph is the region in

which these devices typically do not generate a reset

pulse. This graph was generated using a negative

tude indicated (reset-threshold overdrive). As the mag-

below the reset threshold), the maximum allowable

goes 100mV below the reset threshold and lasts 20µs

or less does not cause a reset pulse to be issued.

MAX6453

MAX6455

RSTIN

R1

R2

RESET

GND

Figure 3. Calculating The Monitored Threshold Voltages