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AN-1177 Datasheet(PDF) 9 Page - Analog Devices |
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AN-1177 Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page Application Note AN-1177 Rev. 0 | Page 9 of 12 part-to-part skew is the greater of these differences (in the case of Figure 18, the difference between the fastest and slowest tPHL). INPUT ACTUAL OUTPUT ACTUAL OUTPUT (2ND) ACTUAL OUTPUT (3RD) ACTUAL OUTPUT (4TH) tPLH(FAST) tPHL(FAST) tPHL(SLOW) tPLH(SLOW) tPLH(SLOW) – tPLH(FAST) tPHL(SLOW) – tPHL(FAST) CHANNEL-TO-CHANNEL OR PART-TO-PART SKEW ( tPHL(SLOW) – tPHL(FAST) > tPLH(SLOW) – tPLH(FAST)) D– D+ D– D+ D– D+ D– D+ D– D+ Figure 18. Waveforms Illustrating Channel-to-Channel or Part-to-Part Skew Both channel-to-channel skew and part-to-part skew result in parallel data channels received out of phase relative to each other, even if they were synchronized at the transmitting end. This can cause difficulties in sampling across multiple channels. DATA ENCODING AND SYNCHRONIZATION The challenges for LVDS timing stem not only from the high speed transmission, but also from the data encoding. In many LVDS applications, in order to increase bandwidth, multiple parallel LVDS channels are used to transmit data. The transmitter must synchronize data transmitted on these channels and the receiver needs to sample each channel at the appropriate point so that data can be received at the same time across channels. In LVDS applications using few channels, serial data is typically transmitted and at higher speeds. The high speed requires the receiving device to synchronize quickly with the incoming data stream, and, in addition to accurately sampling each bit, the receiving device needs to detect frames of data in the incoming bit stream. To help the receiving device synchronize with the received data, a clock may be transmitted with the data channels. This is described as source-synchronous data transmission. There are several methods of transmitting the clock with the data. The clock may be transmitted as a parallel channel, with the clock period corresponding to one data bit (single data rate, SDR) or two data bits (double data rate, DDR). For serial LVDS transmission, a frame clock may also be transmitted. An example of ADC source-synchronous LVDS outputs for SDR and DDR is shown in Figure 19. SAMPLE N SAMPLE N + 2 SAMPLE N + 1 CLK+ SAMPLE N – 7 BIT 0 (LSB) BIT 0 (LSB) BIT 5 BIT 0 (LSB) BIT 5 BIT 9 (MSB) BIT 4 BIT 9 (MSB) BIT 4 SAMPLE N – 7 SAMPLE N – 6 BIT 0 (LSB) CLK– DCO+ DCO– D0+ D0– SAMPLE N – 7 BIT 9 (MSB) SAMPLE N – 6 BIT 9 (MSB) D9+ D9– ANALOG INPUT INTERNAL CLOCK: LVDS OUTPUTS: SDR (10 CHs) DDR (5 CHs) D0/D5+ D0/D5– D4/D9+ D4/D9– SAMPLE N – 6 Figure 19. ADC input and Source-Synchronous LVDS Output Waveforms An alternative to dedicated clock channels is to embed the clock with the data. With the embedded clock method, fixed bits are inserted into the data stream, allowing a receiving node to detect these bits and synchronize with the incoming data. Channel-to-channel and part-to-part skew can be compensated for when received by modern FPGAs, using a scheme termed dynamic phase adjustment (DPA). The FPGA generates multiple phases of the received source-synchronous clock and matches each data channel to the best clock phase for sampling. If DPA is not available, then a strict timing budget must be adhered to. There must be a time interval remaining after transmitter channel-to-channel skew and the sampling time are subtracted from the bit period. This interval is termed the receiver skew margin. The transmitter channel-to-channel skew includes the skew across channels due to the transmitting node, the skew due to the medium and the clock skew relative to the data. |
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