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24LC1025-IP Datasheet(PDF) 8 Page - Microchip Technology |
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24LC1025-IP Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 28 page  24AA1025/24LC1025/24FC1025 DS21941K-page 8 2005-2012 Microchip Technology Inc. 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX1025, this is set as ‘1010’ binary for read and write operations. The next bit of the control byte is the block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of the control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX1025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are in effect the two Most Significant bits (MSb) of the word address. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected, and when set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). The upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the 24XX1025 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX1025 will select a read or write operation. This device has an internal addressing boundary limitation that is divided into two segments of 512K bits. Block select bit ‘B0’ to control access to each segment. FIGURE 5-1: CONTROL BYTE FORMAT 5.1 Contiguous Addressing Across Multiple Devices The Chip Select bits A1 and A0 can be used to expand the contiguous address space for up to 4 Mbit by add- ing up to four 24XX1025’s on the same bus. In this case, software can use A0 of the control byte as address bit A17 and A1 as address bit A18. It is not possible to sequentially read across device boundar- ies. Each device has internal addressing boundary limitations. This divides each part into two segments of 512K bits. The block select bit ‘B0’ controls access to each “half”. Sequential read operations are limited to 512K blocks. To read through four devices on the same bus, eight random Read commands must be given. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS 10 1 0 B0 A1 A0 SACK R/W Control Code Chip Bits Slave Address Acknowledge Bit Start Bit Read/Write Bit Select Block Select Bits 1 010 B 0 A 1 A 0 R/W A 11 A 10 A 9 A 7 A 0 A 8 •• • • •• A 12 Control Byte Address High Byte Address Low Byte Control Code Chip Select Bits X = “don’t care” bit A 13 A 14 Block Select Bit A 15 |
Similar Part No. - 24LC1025-IP |
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Similar Description - 24LC1025-IP |
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